1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming raised source and drain structures without using selective epitaxial silicon growth (SEG).
2) Description of the Prior Art
As semiconductor dimensions continue to shrink and device densities increase, contact resistance and junction depth become increasingly critical to device performance. Raised source and drain structures can provide shallow junctions with low series resistance, enhancing performance. However, raised source and drain structures are typically fabricated using a selective epitaxial silicon growth (SEG) which has several drawbacks. SEG is an expensive process, and it is difficult to control. SEG generally suffers from spurious growth (on isolation structures and layers), incomplete growth (particularly on contaminated surfaces) and faceting.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,899,719 (Hong) shows a method for forming a raised source and drain without SEG by patterning a gate opening in a polysilicon layer doped with impurity ions of as first type, forming source and drain junctions under the polysilicon layer by diffusion, forming dielectric spacers at the edges of the gate opening, and depositing a second polysilicon layer to form a gate electrode. Lightly doped source and drain regions (LDD's) are formed by implanting impurity ions of the first type through the gate opening prior to forming the spacers, then counter-doping the channel region after forming the spacers using impurity ions of a second type opposite the first type. In one embodiment of this invention, the dielectric spacers are removed after the gate electrode is formed, and a halo implant is performed having a conductivity opposite from the source and drain junctions to reduce the size of the junctions, and the spacers are reformed by a second dielectric deposition. However, this invention does not show or suggest forming source and drain extensions (LDD) by implanting through an opening created by removing dielectric spacers adjacent the gate electrode. Nor does this invention show or suggest that it can be used with a self-aligned silicide process, whose rapid thermal anneal step would further difuse the source and drain extensions. Also, this invention does not show or suggest the use of a liner oxide layer.
U.S. Pat. No. 5,915,183 (Gambino et al.) shows a raised source and drain junction process using CMP and a recess etch of a blanket polysilicon layer.
U.S. Pat. No. 5,571,738 (Krivokapic) shows a polysilicon LDD and a self-aligned channel transistor.
U.S. Pat. No. 5,082,794 (Pfiester et al.) teaches selective polysilicon deposition for a transistor.
U.S. Pat. No. 5,827,768 (Lin et al.) shows a planarized and raised source and drain structure.